The embodiments described below involve the developing and ever-expanding field of computer systems and microprocessors. As these fields advance, considerations of efficiencies bear on all aspects of operation and design. One key example of such considerations is device size. Another area is efficiency of microcode. These examples are just some of those which are addressed by the embodiments set forth below. Particularly, these embodiments are directed in many respects to the microprogram memory, which typically in the art is a read only memory referred to as the microROM. The microprogram memory is a fundamental unit of the microprocessor which receives a "microaddress" and, in response, outputs a "microinstruction." The microinstruction is a multiple bit signal, and the value of most if not all of those bits is used to control some aspect of the microprocessor. For example, in horizontal always-branch microprocessors, each microinstruction includes at least one microaddress of the next potential microinstruction to be output by the microprogram memory. As detailed below, microprocessor systems using such a microprogram memory are improved upon by the following embodiments.
In prior art horizontal always-branch microprocessors, the microaddress included within the microinstruction includes three parts: (1) a least significant bit; (2) a next-to-least significant bit; and (3) a main portion. Each of these three portions is concatenated to create the next microaddress for an unconditional branch. In other words, the next microaddress for an unconditional branch is created as shown diagrammatically below:
.vertline.main portion.vertline.next-to-least significant bit.vertline.least significant bit.vertline. PA1 .vertline.main portion.vertline.condition code J.vertline.condition code I.vertline. PA1 .vertline.main portion.vertline.0.vertline.0.vertline. PA1 main portion.vertline.0.vertline.1.vertline. PA1 .vertline.main portion.vertline.1.vertline.0.vertline. PA1 .vertline.main portion.vertline.1.vertline.1.vertline.
In contrast, the next microaddress for a prior art 4-way conditional branch is created by concatenating the main portion with the applicable condition codes and, therefore, the next-to-least significant bit and the least significant from the preceding microinstruction are disregarded. Particularly, the applicable condition codes are substituted in place of the next-to-least significant bit and the least significant and, thus the next microaddress for a conditional branch is:
where "I" and "J" are shown to indicate any given two different condition codes. Thus, the microaddress of the next (or "target") microinstruction depends upon the particular binary values of condition codes I and J.
To implement the above, the prior art hardware configuration for creating a 4-way conditional branch microaddress merely receives the above information, and directly outputs it in the above format. In other words, the values of the condition codes are directly injected into the last two bits of the next microaddress. As a result, for a conditional branch based on two condition codes, there exists the possibility of four different microaddresses. Shown diagrammatically, these microaddresses are:
Further, because of the possibility of four different microaddresses, the prior art microprogram memory necessarily includes four different target microinstructions, that is, one for each of the corresponding microaddresses. Still further, the above describes the instance of a 4-way conditional branch, while it should be noted that various prior art architectures operate in the same manner for conditional branches greater than four, such as an 8-way, 16-way, or even greater conditional branch scenario. In each instance, the prior art microprogram memory necessarily includes a sufficient number of different target microinstructions to accommodate each of the ways (e.g., 8,16, or more) in which the branch can occur.
As detailed below, the inventors of the present embodiments now appreciate various inefficiencies in the above approach including unnecessarily duplicated microinstructions. Therefore, there arises a need to address the drawbacks of current processors, particularly in view of these as well as other inefficiencies.